Figure 1

Current Fuzbien Technology Institute (FTI) CNT-FET. Each 4'' silica semiconductor wafer has forty six 0.45''x 0.15''cells containing 2 independent CNT circuits (upper and lower). An enlarged view of a cell indicating the contact surfaces of the source and the drain is shown to the right of the wafer. Gate voltage is applied at the back of the wafer. Also indicated are the aligning markers for the lithography printing system. Below the cell is a SEM of a circuit showing the CNT's sandwiched between the gold source and drain electrodes.